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LNBH221
Dual LNB supply and control IC with Step-Up converter and IC interface
Feature summary
I I
All the features are the same for both section Complete and independent interface between LNBS and relevant I2CTM BUS BUILT-IN DC/DC controller for single 12V supply operation and high efficiency (Typ. 93% @ 500mA) LNB output current guaranteed up to 500mA Both compliant with eutelsat and directv output voltage specification accurate BUILT-IN 22KHz tone oscillator suits widely accepted standards Fast oscillator start-up facilitates DiSEqCTM encoding BUILT-IN 22KHz tone detector supports bidirectional DiSEqCTM 2.0 Semi-lowdrop post regulator and high efficiency step-up pwm for low power loss: Typ. 0.56W @ 125mA Two output pins suitable to bypass the output rl filter and avoid any tone distorsion (R-L filter as per DiSEqC 2.0 SPECs, see application circuit on pag. 7, 8) Overload and over-temperature internal protections Overload and over-temperature I2C diagnostic BITs LNB short circuit soa protection with I2C diagnostic bit +/- 4KV ESD tolerant on input/output power pins assembled in POWER SO-36, specifically designed to provide the power 13/18V, and the 22KHz tone signalling for two independent LNB down converters or to a multiswitch box that could be independently powered and set. In this application field, it offers a complete solution with extremely low component count, low power dissipation together with simple design and I2CTM standard interfacing.
POWER SO-36
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Description
Intended for analog and digital DUAL Satellite STB receivers/SatTV, sets/PC cards, the LNBH221 is a voltage regulator and interface IC,
February 2006
Rev. 5
1/27
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LNBH221
Contents
1 2 3 4 5 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Typical application circuits for each section : A and B . . . . . . . . . . . . . 7 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 5.2 5.3 5.4 5.5 5.6 I2C Bus Interface (one for each section) . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Transmission without acknowledgement . . . . . . . . . . . . . . . . . . . . . . . . . .11
6
LNBH221 software description (same for both section) . . . . . . . . . . . 13
6.1 6.2 6.3 6.4 6.5 6.6 6.7 Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 System register (SR, 1 Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Transmitted data (I2C BUS write mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Received data (I2C bus READ MODE) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power-On I2C interface reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Address Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DiSEqCTM Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7 8 9 10 11
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Thermal design notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Typical performance characteristics (of each section) . . . . . . . . . . . . 19 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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LD39150
Diagram
1
Figure 1.
Diagram
Block diagram
Gate Sense
Step-up Controller
LNBH221- section A VoTX
Vup Vcc Byp
Preregul.+ U.V.lockout +P.ON res.
VoRX
Linear Post-reg +Modulator +Protections Diagn.
EXTM
SDA SCL ADDR
V Select IC Enable
TEN
DSQIN
22KHz Oscill.
Tone Detector
DETIN DSQOUT
Gate Sense
Step-up Controller
LNBH221- section B VoTX
Vup Vcc Byp
Preregul.+ U.V.lockout +P.ON res.
VoRX
Linear Post-reg +Modulator +Protections Diagn.
EXTM
SDA SCL ADDR
V Select IC Enable
TEN
DSQIN
22KHz Oscill.
Tone Detector
DETIN DSQOUT
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Maximum ratings
LNBH221
2
Table 1.
Symbol VCC VUP VOTX/RX IO VI VDETIN VOH IGATE VSENSE VADDRESS Tstg TJ
Maximum ratings
Absolute maximum ratings
Parameter DC Input Voltage DC Input Voltage DC Output Pin Voltage Output Current Logic Input Voltage (SDA, SCL, DSQIN) Detector Input Signal Amplitude Logic High Output Voltage (DSQOUT) Gate Current Current Sense Voltage Address Pin Voltage Storage Temperature Range Operating Junction Temperature Range Value -0.3 to 16 -0.3 to 25 -0.3 to 25 Internally Limited -0.3 to 7 -0.3 to 2 -0.3 to 7 400 -0.3 to 1 -0.3 to 7 -40 to 150 -40 to 125 Unit V V V mA V VPP V mA V V C C
Note:
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Thermal Data
Parameter Thermal Resistance Junction-Case Value 2 Unit C/W
Table 2.
Symbol RthJC
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LD39150
Pin configuration
3
Figure 2.
Pin configuration
Pin configurations (top view)
Table 3.
Symbol
Pin description
Name Function PIN Number Sect: A B 26 25 24
VCC GATE SENSE
Supply Input External Switch Gate Current Sense (Input)
8V to 15V supply. A 220F bypass capacitor to GND with a 470nF (ceramic) in parallel is recommended. External MOS switch Gate connection of the step-up converter. Current Sense comparator input. Connected to current sensing resistor. Input of the linear post-regulator. The voltage on this pin is monitored by the internal step-up controller to keep a minimum dropout across the linear pass transistor. RX Output to the LNB in DiSEqC 2.0 application. See truth table for voltage selections and description on page 4. Bidirectional data from/to I2C bus. Clock from I2C bus. When the TEN bit of the System Register is LOW, this pin will accept the DiSEqC code from the main controller. Each section of the LNBH221 will use this code to modulate the internally generated 22kHz carrier. Set to GND this pin if not used. 22kHz Tone Detector Input. Must be AC coupled to the DiSEqC bus.
8 7 6
VUP
Step-up Voltage Output Port during 22KHz Tone RX Serial Data Serial Clock
9
27
VORX SDA SCL
28 2 3
10 20 21
DSQIN
DiSEqC Input
4
22
DETIN
Detector In
35
17
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Pin configuration Table 3.
Symbol
LNBH221
Pin description
Name Function PIN Number Sect: A B 23
DSQOUT DiSEqC Output
Open drain output of the Tone Detector to the main controller for DiSEqC data decoding. It is LOW when tone is detected on the DETIN. External Modulation Input. Needs DC decoupling to the AC source. If not used, can be left open.
5
EXTM
External Modulation
31
13
GND
Ground
1, 14, 1, 14, 18, 18, Circuit Ground. It is internally connected to the die frame for heat 19, 19, dissipation. 32, 32, 36 36 34 30 29 33 16 12 11 15
BYP VOTX GND ADDR
Bypass Capacitor pin Needed for internal pre regulator filtering. Output Port during 22KHz Tone TX Ground Address Setting Output of the linear post regulator/modulator to the LNB. See truth table for voltage selections. To be connected to ground. Four I bus addresses available by setting the Address Pin level voltage.
2C
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LD39150
Typical application circuits for each section: A and B
4
Figure 3.
Typical application circuits for each section: A and B
Application Circuit For Diseqc 1.x And Output Current Up To 500mA
Axial Ferrite Bead Filter
F1 suggested part number:
MURATA BL01RN1-A62 Panasonic EXCELS A35
D1 1N4001
IC1
F1
Vup
C9 220F IC2
C2 220F
STS4DNFS30L
C3 470nF Ceramic
VoRX
Set TTX=1
to LNB
Gate
VoTX
LNBH221
L1=22H
Rsc 0.1 C4 470nF Ceramic Vcc Vin 12V C1 220F SDA SCL DSQIN Tone Enable GND EXTM Address DSQOUT Sense (**) DETIN
C5 10nF
D2 BAT43
Section A and B
Byp
C5 470nF
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Typical application circuits for each section: A and B
LNBH221
Figure 4.
Application Circuit For Bi-directional Diseqc 2.0 And Output Current Up To 500mA
F1 suggested part number:
MURATA BL01RN1-A62 Panasonic EXCELS A35
D2 1N4001
Axial Ferrite Bead Filter
IC1
F1
Vup C9 220F IC2 C2 220F C3(***) 470nF Ceramic
VoTX C8(***) 100nF D4(***) BAT43 270H Gate VoRX D3(***) BAT43
STS4DNFS30L
to LNB
LNBH221
L1=22H
Rsc 0.1 Sense (**) DETIN
C7(***) 100nF
15 ohm
(*) see note
Section A and B
Byp Vcc
C6 10nF
Vin 12V
C1 220F
C4(***) 470nF Ceramic
C5 470nF
SDA SCL DSQIN (**) GND
EXTM ADDRESS DSQOUT
022KHz Tone Enable
1. C8, D3 and D4 are needed to protect the output pins from any negative voltage spikes during high speed voltage transitions. 2. (*): R-L filter to be used according to EUTELSAT recommendation to implement the DiSEqCTM 2.0, (see DiSEqCTM implementation on page 8). If bidirectional DiSEqCTM 2.0 is not implemented it can be removed both with C8 and D4. 3. (**) Do not leave these pins floating if not used. 4. (***) To be soldered as close as possible to relative pins
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LD39150
Application information
5
Application information
Basically, the LNBH221 includes two circuits that are completely independent. Each circuit can be separately controlled and must have its independent external components. All the below specification must be considered equal for each section. This IC has a built in DC/DC step-up controller that, from a single supply source ranging from 8 to 15V, generates the voltages (VUP) that let the linear post-regulator to work at a minimum dissipated power of 1W typ. @ 500mA load (the linear regulator drop voltage is internally kept at: VUP-VOUT=2V typ.). An UnderVoltage Lockout circuit will disable the whole circuit when the supplied VCC drops below a fixed threshold (6.7V typically). The internal 22KHz tone generator is factory trimmed in accordance to the standards, and can be controlled either by the I2CTM interface or by a dedicated pin (DSQIN) that allows immediate DiSEqCTM data encoding (*). When the TEN (Tone ENable) I2C bit it is set to HIGH, a continuous 22KHz tone is generated on the output regardless of the DSQIN pin logic status. The TEN bit must be set LOW when the DSQIN pin is used for DiSEqCTM encoding. The fully bi-directional DiSEqCTM 2.0 interfacing is completed by the built-in 22KHz tone detector. Its input pin (DETIN) must be AC coupled to the DiSEqCTM bus, and the extracted PWK data are available on the DSQOUT pin (*). To comply to the bi-directional DiSEqCTM 2.0 bus hardware requirements an output R-L filter is needed. The LNBH221 is provided with two output pins: the VOTX to be used during the tone transmission and the VORX to be used when the tone is received. This allows the 22KHz Tone to pass without any losses due to the R-L filter impedance (see DiSeqC 2.0 application circuit on page 4). In DiSeqC 2.0 applications during the 22KHz transmission activated by DSQIN pin (or TEN I2C bit), the VOTX pin must be preventively set ON by the TTX I2C bit and, both the 13/18V power supply and the 22KHz tone, are provided by mean of VOTX output. As soon as the tone transmission is expired, the VOTX must be set to OFF by setting the TTX I2C bit to zero and the 13/18V power supply is provided to the LNB by the VORX pin through the R-L filter. When the LNBH221 is used in DiSeqC 1.x applications the R-L filter is not required (see DiSeqC 1.x application circuit on pag. 4), the TTX I2C bit must be kept always to HIGH so that, the VOTX output pin can provide both the 13/18V power supply and the 22KHz tone, enabled by DSQIN pin or by TEN I2C bit. All the functions of this IC are controlled via I2CTM bus by writing 6 bits on the System Register (SR, 8 bits). The same register can be read back, and two bits will report the diagnostic status. When the IC is put in Stand-by (EN bit LOW), the power blocks are disabled. When the regulator blocks are active (EN bit HIGH), the output can be logic controlled to be 13 or 18V by mean of the VSEL bit (Voltage SELect) for remote controlling of non-DiSEqC LNBs. Additionally, the LNBH221 is provided with the LLC I2C bit that increase the selected voltage value (+1V when VSEL=0 and +1.5V when VSEL=1) to compensate for the excess voltage drop along the coaxial cable (LLC bit HIGH). By mean of the LLC bit, the LNBH221 is also compliant to the American LNB power supply standards that require the higher output voltage level to 19.5V (typ.) (instead of 18V), by simply setting the LLC=1 when VSEL=1. In order to improve design flexibility and to allow implementation of newcoming LNB remote control standards, an analogic modulation input pin is available (EXTM). An appropriate DC blocking capacitor must be used to couple the modulating signal source to the EXTM pin. Also in this case, the VOTX output must be set ON during the tone transmission by setting the TTX bit high. When external modulation is not used, the relevant pin can be left open. The current limitation block is SOA type: if the output port is shorted to ground, the SOA current limitation block limits the short circuit current (ISC) at typically 300mA or 200mA respectively for VOUT 13V or 18V, to reduce the power dissipation.
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Application information
LNBH221
Moreover, it is possible to set the Short Circuit Current protection either statically (simple current clamp) or dynamically by the PCL bit of the I2C SR; when the PCL (Pulsed Current Limiting) bit is set to LOW, the overcurrent protection circuit works dynamically, as soon as an overload is detected, the output is shut-down for a time TOFF, typically 900ms. Simultaneously the OLF bit of the System Register is set to HIGH. After this time has elapsed, the output is resumed for a time TON=1/10TOFF (typ.). At the end of TON, if the overload is still detected, the protection circuit will cycle again through TOFF and TON. At the end of a full TON in which no overload is detected, normal operation is resumed and the OLF bit is reset to LOW. Typical TON+TOFF time is 990ms and it is determined by an internal timer. This dynamic operation can greatly reduce the power dissipation in short circuit condition, still ensuring excellent power-on start up in most conditions. However, there could be some cases in which an highly capacitive load on the output may cause a difficult startup when the dynamic protection is chosen. This can be solved by initiating any power startup in static mode (PCL=HIGH) and then switching to the dynamic mode (PCL=LOW) after a chosen amount of time. When in static mode, the OLF bit goes HIGH when the current clamp limit is reached and returns LOW when the overload condition is cleared. This IC is also protected against overheating: when the junction temperature exceeds 150C (typ.), the step-up converter and the linear regulator are shut off, and the OTF SR bit is set to HIGH. Normal operation is resumed and the OTF bit is reset to LOW when the junction is cooled down to 140C (typ.). Note: (*): External components are needed to comply to bi-directional DiSEqCTM bus hardware requirements. Full compliance of the whole application to DiSEqCTM specifications is not implied by the use of this IC. NOTICE: DiSEqC is a trademark of EUTELSAT. I2C is a trademark of Philips Semiconductors.
Note:
5.1
I2C Bus Interface (one for each section)
Data transmission from main P to the LNBH221 and viceversa takes place through the 2 wires I2C bus interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected).
5.2
Data validity
As shown in Figure 5., the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
5.3
Start and stop conditions
As shown in Figure 6. a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP conditions must be sent before each START condition.
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LD39150
Application information
5.4
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first.
5.5
Acknowledge
The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see Figure 7.). The peripheral (LNBH221) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The peripheral which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. The LNBH221 won't generate the acknowledge if the VCC supply is below the Undervoltage Lockout threshold (6.7V typ.).
5.6
Transmission without acknowledgement
Avoiding to detect the acknowledge of the LNBH221, the P can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity..
Figure 5.
Data Validity On The I2C Bus
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Application information . Figure 6. Timing Diagram On I2C Bus
LNBH221
Figure 7.
Acknowledge On I2C Bus
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LD39150
LNBH221 software description (same for both section)
6
LNBH221 software description (same for both section)
Interface Protocol
The interface protocol comprises: - A start condition (S) - A chip address byte = hex 10 / 11 (the LSB bit determines read(=1)/write(=0) transmission) - A sequence of data (1 byte + acknowledge) - A stop condition (P)
CHIP ADDRESS MSB 0 0 LSB R/W ACK MSB DATA LSB ACK P
6.1
S
0
1
0
0
0
ACK= Acknowledge S= Start P= Stop R/W= Read/Write
6.2
MSB R, W PCL
System register (SR, 1 Byte)
R, W TTX
R= Read-only bit All bits reset to 0 at Power-On
R, W TEN
R, W LLC
R, W VSEL
R, W EN
R OTF
LSB R OLF
R,W= read and write bit
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LNBH221 software description (same for both section)
LNBH221
6.3
Transmitted data (I2C BUS write mode)
When the R/W bit in the chip address is set to 0, the main P can write on the System Register (SR) of the LNBH221 via I2C bus. Only 6 bits out of the 8 available can be written by the P, since the remaining 2 are left to the diagnostic flags, and are read-only.
PCL
TTX
TEN
LLC VSEL 0 0 1 1 0 1 0 1
EN 1 1 1 1 1 1 1
OTF X X X X X X X X X X X
OLF X X X X X X X X X X X
Function VOUT=13.25V, VUP=15.25V VOUT=18V, VUP=20V VOUT=14.25V, VUP=16.25V VOUT=19.5V, VUP=21.5V 22KHz tone is controlled by DSQIN pin 22KHz tone is ON, DSQIN pin disabled VORX output is ON, output voltage controlled by VSEL and LLC VOTX output is ON, 22KHz controlled by DSQIN or TEN, output voltage level controlled by VSEL and LLC Pulsed (dynamic) current limiting is selected Static current limiting is selected Power blocks disabled
0 1 0 1 0 1 X X
1 1 1 0
X
X
X
X
X= don't care. Values are typical unless otherwise specified.
6.4
Received data (I2C bus READ MODE)
The LNBH221 can provide to the Master a copy of the SYSTEM REGISTER information via I2C bus in read mode. The read mode is Master activated by sending the chip address with R/W bit set to 1. At the following master generated clocks bits, the LNBH221 issues a byte on the SDA data bus line (MSB transmitted first). At the ninth clock bit the MCU master can: - acknowledge the reception, starting in this way the transmission of another byte from the LNBH221; - no acknowledge, stopping the read mode communication. While the whole register is read back by the P, only the two read-only bits OLF and OTF convey diagnostic informations about the LNBH221.
PCL
ISEL
TEN
LLC VSEL
EN
OTF 0 1
OLF
Function TJ<140C, normal operation TJ>150C, power block disabled IOUTIOMAX, overload protection triggered
These bits are read exactly the same as they were left after last write operation
0 1
Values are typical unless otherwise specified.
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LD39150
LNBH221 software description (same for both section)
6.5
Power-On I2C interface reset
The I2C interface built in the LNBH221 is automatically reset at power-on. As long as the VCC stays below the UnderVoltage Lockout threshold (6.7V typ.), the interface will not respond to any I2C command and the System Register (SR) is initialized to all zeroes, thus keeping the power blocks disabled. Once the VCC rises above 7.3V typ, the I2C interface becomes operative and the SR can be configured by the main P. This is due to 500mV of hysteresis provided in the UVL threshold to avoid false retriggering of the Power-On reset circuit.
6.6
Address Pin
Connecting this pin to GND the Chip I2C interface address is 0001000, but, it is possible to choice among 4 different addresses simply setting this pin at 4 fixed voltage levels (see Table 7. on page 17).
6.7
DiSEqCTM Implementation
The LNBH221 helps the system designer to implement the bi-directional DiSEqC 2.0 protocol by allowing an easy PWK modulation/demodulation of the 22KHz carrier. The PWK data are exchanged between the LNBH221 and the main P using logic levels that are compatible with both 3.3 and 5V microcontrollers. This data exchange is made through two dedicated pins, DSQIN and DSQOUT, in order to maintain the timing relationships between the PWK data and the PWK modulation as accurate as possible. These two pins should be directly connected to two I/O pins of the P, thus leaving to the resident firmware the task of encoding and decoding the PWK data in accordance to the DiSEqC protocol. Full compliance of the system to the specification is thus not implied by the bare use of the LNBH221. The system designer should also take in consideration the bus hardware requirements; that can be simply accomplished by the R-L termination connected on the VOUT pins of the LNBH221, as shown in the Typical Application Circuit on page 7, 8. To avoid any losses due to the R-L impedance during the tone transmission, the LNBH221 has dedicated output (VOTX) that, in a DiSEqC 2.0 application, is connected after the filter and must be enabled by setting the TTX SR bit HIGH only during the tone transmission (see DiSEqC 2.O operation description on page 9). Unidirectional (1.x) DiSEqC and non-DiSEqC systems normally don't need this termination, and the VOTX pin can be directly connected to the LNB supply port of the Tuner (see DiSeqC 1.x application circuit on pag. 7, 8). There is also no need of Tone Decoding, thus DETIN and DSQOUT pins can be left unconnected and the Tone is provided by the VOTX.
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Electrical characteristics
LNBH221
7
Table 4.
Electrical characteristics
Electrical characteristics of each section (A and B) (TJ = 0 to 85C, EN=1, TTX=0/1, LLC=VSEL=TEN=PCL=0, DSQIN=LOW, VIN=12V, IOUT=50mA, unless otherwise specified. See software description section for I2C access to the system register)
Symbol VIN Parameter Supply Voltage Parameter IOUT = 500 mA TEN=VSEL=LLC=1 EN=TEN=VSEL=LLC=1, No Load EN=0 VOUT Output Voltage IOUT = 500 mA VSEL=1 IO = 500 mA VSEL=0 VIN =8 to 15V LLC=0 LLC=1 LLC=0 LLC=1 VSEL=0 Line Regulation VSEL=1 17.3 18.7 Min. 8 20 3.5 18 19.5 Typ. Max. 15 40 mA 7 18.7 V 20.3 V 13.75 14.25 14.75 5 5 40 mV 60 200 500 VSEL = 0 ISC tOFF tON fTONE ATONE DTONE tr, tf GEXTM VEXTM ZEXTM fSW fDETIN Output Short Circuit Current VSEL = 1 Dynamic Overload protection OFF Time Dynamic Overload protection ON Time Tone Frequency Tone Amplitude Tone Duty Cycle Tone Rise and Fall Time External Modulation Gain External Modulation Input Voltage PCL=0Output Shorted PCL=0Output Shorted TEN=1 TEN=1 TEN=1 TEN=1 VOUT/VEXTM, f = 10Hz to 50KHz, TTX=1 AC Coupling, TTX=1 260 220 0.4Vpp sinewave 18 24 20 0.55 40 5 200 900 tOFF/1 0 22 0.72 50 8 6 400 mVPP W kHz kHz 24 0.9 60 15 ms ms KHz VPP % s 300 mA 750 mV mA 12.75 13.25 13.75 Unit V
IIN
Supply Current
VOUT VOUT VOUT IMAX
Output Voltage
Load Regulation Output Current Limiting
VSEL = 0 or 1 IOUT = 50 to 500mA
External Modulation Impedance f = 10Hz to 50KHz DC/DC Converter Switch Frequency Tone Detector Frequency Capture Range
16/27
LD39150 Table 4.
Electrical characteristics Electrical characteristics of each section (A and B) (TJ = 0 to 85C, EN=1, TTX=0/1, LLC=VSEL=TEN=PCL=0, DSQIN=LOW, VIN=12V, IOUT=50mA, unless otherwise specified. See software description section for I2C access to the system register)
Symbol VDETIN ZDETIN VOL IOZ VIL VIH IIH IOBK TSHDN TSHDN
Parameter Tone Detector Input Amplitude Tone Detector Input Impedance DSQOUT Pin Logic LOW DSQOUT Pin Leakage Current DSQIN Input Pin Logic LOW DSQIN Input Pin Logic HIGH DSQIN Pin Input Current Output Backward Current Thermal Shutdown Threshold Thermal Shutdown Hysteresis VIH = 5V
Parameter fIN=22kHz sinewave
Min. 0.2
Typ.
Max. 1.5
Unit VPP k
150 Tone presentIOL=2mA Tone absentVOH = 6V 0.3 0.5 10 0.8 2 15 -6 150 15 -15
V A V V A mA C C
EN=0 VOBK = 18V
Table 5.
Symbol RDSON-L RDSON-H VSENSE
Gate And Sense Electrical Characteristics (TJ = 0 to 85C, VIN=12V)
Parameter Gate LOW RDSON Gate LOW RDSON Current Limit Sense Voltage Parameter IGATE=-100mA IGATE=100mA Min. Typ. 4.5 4.5 200 Max. Unit mV
Table 6.
Symbol VIL VIH IIN VOL fMAX
I2C Electrical Characteristics (TJ = 0 to 85C, VIN=12V)
Parameter LOW Level Input Voltage HIGH Level Input Voltage Input Current Low Level Output Voltage Maximum Clock Frequency SDA, SCL SDA, SCL SDA, SCL, VIN= 0.4 to 4.5V SDA (open drain), IOL = 6mA SCL 500 2 -10 10 0.6 Parameter Min. Typ. Max. 0.8 Unit V V A V KHz
Table 7.
Symbol VADDR-1 VADDR-2 VADDR-3 VADDR-4 VADDR-1
Address Pin Characteristics (TJ = 0 to 85C, VIN=12V)
Parameter "0001000" Addr Pin Voltage "0001001" Addr Pin Voltage "0001010" Addr Pin Voltage "0001011" Addr Pin Voltage "0001000" Addr Pin Voltage Parameter Min. 0 1.3 2.3 3.3 0 Typ. Max. 0.7 1.7 2.7 5 0.7 Unit V V V V V
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Thermal design notes
LNBH221
8
Thermal design notes
During normal operation, the LNBH221 device dissipates some power. At rated output current of 500mA on each section output, the voltage drop on both linear regulators lead to a total dissipated power that is typically 2W. The heat generated requires a suitable heatsink to keep the junction temperature below the over-temperature protection threshold. Assuming a 45C temperature inside the Set-Top-Box case, the total RthJC has to be less than 40C/W. While this can be easily achieved using a through-hole power package that can be attached to a small heatsink or to the metallic frame of the receiver, a surface mount power package must rely on PCB solutions whose thermal efficiency is often limited. The simplest solution is to use a large, continuous copper area of the GND layer to dissipate the heat coming from the IC body. Given for the PSO-36 package an RthJC equal to 2C/W, a maximum of 38C/W are left to the PCB heatsink. This area can be the inner GND layer of a multi-layer PCB, or, in a dual layer PCB, an unbroken GND area even on the opposite side where the IC is placed. In Figure 8., it is shown a suggested layout for the PSO-36 package with a dual layer PCB, where the IC exposed pad connected to GND and the square dissipating area are thermally connected through 32 vias holes, filled by solder. This arrangement, when L=40mm, achieves an RthJA of about 28C/W. Different layouts are possible, too. Basic principles, however, suggest to keep the IC and its ground exposed pad approximately in the middle of the dissipating area; to provide as many vias as possible; to design a dissipating area having a shape as square as possible and not interrupted by other copper traces.
Figure 8.
PowerSO-36 Suggested Pcb Heatsink Layout
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LD39150
Typical performance characteristics (of each section)
9
Typical performance characteristics (of each section)
(TJ = 25C, unless otherwise specification)
Figure 9.
Output Voltage vs Temperature
Figure 10. Output Voltage vs Temperature
Figure 11. Output Voltage vs Temperature
Figure 12. Load Regulation vs Temperature
Figure 13. Load Regulation vs Temperature
Figure 14. Supply Current vs Temperature
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Typical performance characteristics (of each section)
LNBH221
Figure 15. Supply Current vs Temperature
Figure 16. Supply Current vs Temperature
Figure 17. Dynamic Overload Protection ON Time vs Temperature
Figure 18. Dynamic Overload Protection OFF Time vs Temperature
Figure 19. Output Current Limiting vs Temperature
Figure 20. Tone Frequency vs Temperature
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LD39150
Typical performance characteristics (of each section)
Figure 21. Tone Amplitude vs Temperature
Figure 22. Tone Duty Cycle vs Temperature
Figure 23. Tone Rise Time vs Temperature
Figure 24. Tone Fall Time vs Temperature
Figure 25. Undervoltage Lockout Threshold vs Figure 26. Output Backward Current vs Temperature Temperature
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Typical performance characteristics (of each section)
LNBH221
Figure 27. DC/DC Converter Efficiency vs Temperature
Figure 28. Current Limit Sense Voltage vs Temperature
Figure 29. 22kHz Tone Waveform
Figure 30. DSQIN Tone Enable Transient Response
VCC=12V, IO=50mA, EN=TEN=1
VCC=12V, IO=50mA, EN=1, Tone enabled by DSQIN Pin
Figure 31. DSQIN Tone Enable Transient Response
Figure 32. DSQIN Tone Disable Transient Response
VCC=12V, IO=50mA, EN=1, Tone enabled by DSQIN Pin
VCC=12V, IO=50mA, EN=1, Tone enabled by DSQIN Pin
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Package mechanical data
10
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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Package mechanical data
LNBH221
PowerSO-36 MECHANICAL DATA
DIM. A a1 a2 a3 b c D (1) D1 E E1 (1) E2 E3 e e3 G H h L N S mm. MIN. 0.10 0 0.22 0.23 15.80 9.40 13.90 10.90 5.8 0.65 11.05 0 15.50 0.80 0

inch MAX. 3.60 0.30 3.30 0.10 0.38 0.32 16.00 9.80 14.50 11.10 2.90 6.2 MIN. 0.0039 0 0.0087 0.0091 0.6220 0.3701 0.5472 0.4291 0.2283 0.0256 0.4350 0.10 15.90 1.10 1.10 10 8 0.0000 0.6102 0.0315

TYP
TYP.
MAX. 0.1417 0.0118 0.1299 0.0039 0.0150 0.0126 0.6299 0.3858 0.5709 0.4370 0.1142 0.2441
0

0.0039 0.6260 0.0433 0.0433 10 8
6 (1) " and E1" do not include mold flash or protusions - Mold flash or protusions shall not exceed 0.15mm (0.00 ") D
0096119/B
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LD39150
Package mechanical data
Tape & Reel PowerSO-36 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P W 15.1 16.5 3.8 3.9 23.9 23.7 12.8 20.2 60 30.4 15.3 16.7 4.0 4.1 24.1 24.3 0.594 0.650 0.149 0.153 0.941 0.933 TYP MAX. 330 13.2 0.504 0.795 2.362 1.197 0.602 0.658 0.157 0.161 0.949 0.957 MIN. TYP. MAX. 12.992 0.519 inch
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Revision history
LNBH221
11
Table 8.
Date
Revision history
Document revision history
Revision 4 5 Maturity Changed. The Figure 3. and Figure 4. has been updated. Changes
08-Apr-2005 23-Feb-2006
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LD39150
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